The present invention generally relates to semiconductor devices, and more particularly to semiconductor devices including conductive lines and vias and methods of forming the same.
Lithographic alignment of vias and conductive lines can occur through thick, opaque conductive films (e.g., metal films). At small dimensions, overlay and alignment errors can have a large impact on via contact resistance and dielectric barriers. Critical dimension (CD) variation can introduce additional overlay and alignment fluctuation. For example, the CD of the via can be smaller than the CD of the conductive line (e.g., either the via is too small or the conductive line is too large), the CD of the via can be larger than the CD of the conductive line (e.g., either the via is too large or the conductive line is too small), or misalignment can occur between a via and conductive line (e.g., a via and conductive line having a substantially similar CD) leading to a reduced contact area.